Shows readers how to gain the competitive edge in the integrated circuit marketplace This book offers a wholly unique perspective on the digital design kit. It points to hidden value in the safety margins of standard-cell libraries and shows design engineers and managers how to use this knowledge to beat the competition. Engineering the CMOS Library reveals step by step how the generic, foundry-provided standard-cell library is built, and how to extract value from existing std-cells and EDA tools in order to produce tighter-margined, smaller, faster, less power-hungry, and more yield-producing integrated circuits. It explores all aspects of the digital design kit, including the different views of CMOS std-cell libraries along with coverage of IO libraries, memory compilers, and small analog blocks. Readers will learn: How to work with overdesigned std-cell libraries to improve profitability while maintaining safety How functions usually found in std-cell libraries cover the design environment, and how to add any missing functions How to harness the characterization technique used by vendors to add characterization without having to get it from the vendor How to use verification and validation techniques to ensure proper descriptive views and even fix inconsistencies in vendor release views How to correct for possible conflicts arising from multiple versions and different vendor sources in any given integrated circuit design Complete with real-world case studies, examples, and suggestions for further research, Engineering the CMOS Library will help readers become more astute designers.

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Engineering the CMOS Library. Enhancing Digital Design Kits for Competitive Silicon